MAKEFILE  TO  COMPILE  FILES  FOR  MODELSIM

A script file can be written to compile source code for simulation. 
Below is the format of a script file that compiles four Verilog source code files.         

#!/bin/tcsh
vlog file1.vl
echo "Press Enter to continue."
read answer
vlog file2.vl
echo "Press Enter to continue."
read answer
vlog file3.vl
echo "Press Enter to continue."
read answer
vlog file4.vl

To run your script file,

1. The file is placed in the directory in which the simulator is run. 



2. The
   chmod u+x filename
   command is typed at the unix prompt.



3. The
   prep mentor
   command is typed at the unix prompt.



4. The
   vlib work
   command is typed at the unix prompt.



5. The file is executed by typing the name of the file at the unix prompt.