Verilog   bitwise   and   logical   negation   operators

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There are two negation operators:

• logical negation !
  Inverts only least significant bit.
  i.e.,   a  =  00;   b =  ! a =  01;
  
  
• bitwise negation ~
  Inverts all bits.
  i.e.,   a  =  00;   c  =  ~ a  =  11;
  
  
• 2.bit.negation.vl
• tb.2.bit.negation.vl