INTEGER  TYPE  NOTE The vhdl integer type range is -2,147,483,647 to 2,147,483,647. The maximum possible integer value, 2,147,483,647, can be represented         in binary by thirty-one 1's, "1111111111111111111111111111111". If an integer type is mapped to hardware in synthesis, it will be synthesized as a 32 bit bus or register unless the integer range is constrained. To constrain the integer range to non-negative integers, one can specify, integer range 0 to 2147483647, i.e., the signal b_out in integer.example.vhd To limit the size of the bus or register used in synthesis to 5 bits, the constraint would be, integer range 0 to 31. Conversion from std_ulogic_vector to integer is also shown in integer.example.vhd.