STATE  MACHINE  DESIGN  STYLES One unclocked process and one clocked process. One unclocked process to assign output and assign next state. One clocked process to update state register. moore1.vhd tb_moore1.vhd Two processes and a concurrent signal assignment. One unclocked process to assign next state. One clocked process to update state register. One concurrent signal assignment statement to assign output.                 moore2.vhd tb_moore2.vhd Two clocked processes and one unclocked process. One clocked process to update state register. One unclocked process to assign next state. One clocked process to register output. moore3.vhd tb_moore3.vhd One clocked process. moore4.vhd tb_moore4.vhd Two unclocked processes and one clocked process. One unclocked process to assign output. One unclocked process to assign next state. One clocked process to update state register. moore5.vhd tb_moore5.vhd