1 `timescale 1ns/1ns
2 module tb_swallace;
3
4
5 reg signed [8:0] a;
6 reg signed [6:0] b;
7 wire signed [15:0] product;
8 reg signed [15:0] check;
9 reg [9:0] i,mdlul;
10 reg [7:0] j,mrlul;
11
12 s_wallace s_wall0(a,b,product);
13
14 initial
15 begin
16 a=-9'd256;
17 b=-7'd64;
18 mrlul=8'd128;
19 mdlul=10'd512;
20 for (i=0;i<mdlul;i=i+1)
21 begin
22 for (j=0;j<mrlul;j=j+1)
23 begin
24 check=$signed(a)*$signed(b);
25 #1;
26 if (product != check)
27 begin
28 $display("time=%0t", $time);
29 $display("a =%0d, b=%0d", a, b);
30 $display("product=%0d, check=%0d", product, check);
31 $finish;
32 end
33 b=b+1'b1;
34 end
35 a=a+1'b1;
36 end
37 $display(" All %0d were correct.\n", 65536);
38 $finish;
39 end
40
41 endmodule