1. Preparation: Unix paths
2. VHDL Source Code
3. Simulation: Modelsim vsim
4. Four-bit adder using the + operator
5. Four-bit adder using a process
6. Delta cycles and processes
7. Built-in functions
8. FSMs
9. A counter example
10. A register file example
11. Functional rtl
12. A few notes
13. Synthesis Preparation and Startup
14. Specification and Loading of the Technology Library
15. Reading in Your VHDL Source Files
16. Optimization
17. Writing an EDIF File
18. The Resource Report
19. The Delay Report
20. Synthesis Script Method
21. Xilinx placement and routing
22. Backannotated gate-level simulation

1.  Preparation: Unix paths

• Open a xterm window
• cd  ~
• mkdir tutorial
• cd tutorial

2.  VHDL Source Code

• vi. 
• gvim.
• xemacs.
• emacs
• pico.

VHDL source code is plain text contained in a single file or a group of files.  VHDL text files use the file extension, .vhd .

• VHDL source code for 1-bit full adder is contained in the file, full.adder.vhd.  Libraries and packages used are declared at the top of the file. The "library ieee;" and "use ieee.std_logic_1164.all;" declarations should always be included in your vhdl files.  The basic building block in VHDL is the entity.  The name of this entity is full_adder.  Comments in VHDL source code are prefaced by --.  The entity interface is coded in the port section of the file.  The entity behavior is coded in the architecture section of the file.  VHDL is case-insensitive and is a strongly-typed language.  The port signal a_one is declared to be an in port.  The two most common types of port signals are of type in and out.  Port signals of type in can only be read in the architecture whereas out ports signals can only be written to.  In other words, signals of type in can only be on the right-hand side of an assignment operator, whereas port signals of type out can only be on the left-hand side of an assignment operator.  A third type of port is inout.  An inout port can be both written to and read from.  The port signal c_in in full.adder.vhd is declared to be of type std_ulogic.  Std_ulogic_vector is an array of type std_ulogic.  Signals of type std_ulogic can take any of nine logic values:
  
  
  1. 'U'  Uninitialized
  2. 'X'  Strong unknown
  3. 'W'  Weak unknown
  4. '0'  Strong 0
  5. 'L'  Weak 0
  6. '1'  Strong 1
  7. 'H'  Weak 1
  8. 'Z'  High Impedance
  9. '-'  Don't care

  The type std_ulogic, (and it's vector representation, std_ulogic_vector), is an unresolved type.  The type std_logic, ( and it's vector representation, std_logic_vector), is a resolved type.  The unresolved type std_ulogic and std_ulogic_vector catches the error of multiple drivers on a signal in the compilation phase of design.  Using std_logic and std_logic_vector would not enable a design tool to detect the problem until simulation or synthesis.  The type std_logic is used in p2.std.logic.vhd and the type std_ulogic is used in p2.std.ulogic.vhd.  The signal z has multiple drivers (z is being assigned to from more than one signal).  The drivers of z are the signals, x and y.  The entity that uses std_logic will pass compilation; the entity that uses std_ulogic does not, enabling earlier detection of an error in the design process.  Testing the entity in p2.std.logic.vhd with the testbench entity in tb.p2.vhd, the std_logic signal z is assigned 'X' when driven by a '0' and a '1'; the std_logic_1164 package contains a resolution table which determines the value a std_logic signal will get when driven by multiple signals.  You can use std_logic (and std_logic_vector) or std_ulogic (and std_ulogic_vector).

• VHDL source code for a hierarchical 4-bit adder is contained in the file, h.4.bit.adder.vhd.  This entity instantiates the full adder four times to construct the 4-bit adder.  Three signals are declared to be used as wires to connect the four instantiations of the full adder together to obtain the four-bit adder.  The carry-out of each of the three lowest bit adders are each connected to the carry-in of the next highest bit adder.   The wiring together of the four 1-bit adders is done by explicit port mapping.  Explicit port mapping has the syntax, formal => actual, in the instantiations of the full adder. The formal parameter is a signal from the port of the full adder.   The actual parameter is a signal from either the port of the h_4_bit_adder entity or from the set of three wires declared in the h_4_bit_adder entity.   Each instantiation of a full adder is given a unique name, i.e., fa0.



• VHDL source code for the testbench for testing the hierachical 4-bit adder entity in h.4.bit.adder.vhd is contained in the file, tb.h4ba.vhd.  A testbench is for simulation only and is not synthesizable (mapable to hardware by a synthesis tool).  The testbench instantiates h_4_bit_adder as a component and applies test vectors, which are input values, to the component in a sequential manner using a process construct.  Since we don't synthesize the testbench, we can use the full range of the VHDL language in a testbench, whereas for a VHDL design that we are going to synthesize, we can only use the subset of the VHDL language that is synthesizable.  For example, "wait for 15 ns", is not synthesizable, but we can use it in a testbench since we are not going to synthesize it. 
  The testbench entity in tb.h4ba.vhd contains three sets of test vectors.  Test vectors are different combinations of input values to test whether your design outputs the expected values.   For example, addend_one <="1011"; addend_two <="1000"; carry-in <='1'; would be one possible combination of inputs.



• Copy the file, full.adder.vhd, to the path ~/tutorial/full.adder.vhd.
  A method for doing for copying the file, full.adder.vhd, assuming that you have started netscape from the path ~/tutorial and have full.adder.vhd in your netscape window, is to choose from the netscape menu, File | Save As ..., and when the Save As... window opens, click the ok button.



• Copy the file, h.4.bit.adder.vhd, to the path ~/tutorial/h.4.bit.adder.vhd.



• Copy the file, tb.h4ba.vhd, to the path ~/tutorial/tb.h4ba.vhd.

3.  Simulation: Modelsim vsim

• Open an xterm window
• cd  ~/tutorial
• tcsh
• prep mentor
• vlib work
  

This creates a ModelSim library named work.  A ModelSim library is a directory that contains the compiled entities.

1. vcom full.adder.vhd  -explicit
   The -explicit option is not needed here, but some students may prefer to use it each time they compile.
2. vcom h.4.bit.adder.vhd
3. vcom tb.h4ba.vhd

• vdir

• vsim  tb_h4ba  -coverage
  The command
  vsim tb_h4ba
  would be ok without the -coverage option if you did not want to use the code coverage feature.  The -coverage option is required to enable the code coverage feature which can sometimes be helpful in debugging.
  The ModelSim Main window opens.
  The entity tb_h4ba is loaded by vsim from the work library.
  Close the workspace subwindow in the ModelSim window by selecting
  View | Workspace
  from the ModelSim menu.
  

In Modelsim,

1. To set the environment workspace to the instantiation of the h_4_bit_adder entity named uut, from the ModelSim Main (transcript) window menu, select View | Structure.  The stucture window will open.  In the structure window, select uut.
   
   
2. To view the signals window, from the ModelSim Main (transcript) window menu, choose View | Signals.
   
   
3. To view the wave window, from the ModelSim Main window menu, choose View | Wave.
   
   
4. From the signals window menu, choose Add | Wave | Signals in Region. 
   The h_4_bit_adder entity signals will be placed in the wave window. 
   Use the left mouse button to move the vertical divider lines in the wave window so that you can read the names of all the signals.
   
   
5. To run the simulation for 60 ns, enter
   run 60
   at the ModelSim prompt in the Modelsim Main window.
   
   
6. In the wave window, to zoom in, from the wave window menu, select View | Zoom | Zoom In.
   
   
7. In the wave window, to change the radix to unsigned, from the wave window menu, first select Edit | Select All
   Then, from the wave window menu, select Format | Radix | Unsigned.
   Then, from the wave window menu, select Edit | Unselect All.
   
   
8. On a waveform in the wave window, click the left mouse button to obtain a marker.
   
   
9. To restart the run, from the ModelSim Main window menu, choose Simulate | Run | Restart..., and when the Restart window appears, select the Restart button.
   
   
10. To run the simulation for 100 ns, enter  run 100  at the ModelSim prompt in the Modelsim Main window.
    
    
11. To delete the signals presently listed in the wave window, from the wave menu choose Edit | Select All.  Then from the wave menu choose Edit | Cut.
    
    
12. When you want to quit ModelSim vsim, from the ModelSim Main window menu, choose File | Quit

The keyboard arrow keys can be used to execute previous commands. A few common vsim questions:

1. How can I display signals from an entity instantiated as a component in my design on the wave diagram when running vsim?
   
   
2. How can I set a breakpoint when running vsim?
   
   
3. How can I obtain code coverage information in ModelSim?
   
   
4. How can I view a variable in a process in the ModelSim wave or list window?
   
   
5. How can I run ModelSim in command-line mode?

You may want to occasionally print out the simulation results that appear in the wave window.  You can use the zoom feature from the wave menu to obtain the proper zoom.  To print the wave, from the wave menu, select File | Print Postscript...  When the Write Postscript window opens, click File name: and type in a name for the file name, i.e., wave1.ps, and click ok.   Only the portion of the wave that is presently viewable will be printed out.  If the waveform is long, you will have to use more than one page.  To set the laser printer destination, in a xterm window, use the command, setenv PRINTER printername  To view and print out a postscript file, you can use ghostview by typing the command, ghostview wave1.ps in a xterm window, where wave1.ps is the name of your postscript file.  To print out the postscript file in ghostview, choose File | Print..., type in the name of the printer in the popup window and click ok.

4.  Four-bit adder using the + operator

1. An example of a 4-bit adder using the '+' operator is, plus.sign.adder.vhd.  This source code contains an entity called easy_adder.  This adder has two 4-bit addend std_ulogic_vector inputs and a 4-bit sum std_ulogic_vector output.  The two addends are added using the + operator.  The numeric_std package is listed in the package declaration section at the top of the code as it is required for the + operator use.  To use the + operator an explicit conversion to type unsigned is done on the two addends and an explicit conversion to type std_ulogic_vector is done on the result of the addition. Additions using the + operator with two four-bit addends are modulo-16.  The msb carry-out is truncated.  A testbench to test the easy_adder entity is the tb_psa entity in the file, tb.psa.vhd   
   • An example of the use of a for loop to produce test vectors to test the adder is the testbench in, tb.psa1.1.vhd. 


2. plus.sign.adder2.vhd: In this file, the entity easy_adder2 has two four-bit addends that are each concatenated with a '0' in the msb before they are added.  The result of the addition will be five bits, so the result can be assigned to the five-bit sum. A testbench to test the easy_adder2 entity is the tb_psa2 entity in the file, tb.psa2.vhd. 

5.  Four-bit adder using an unclocked process

The VHDL code of the 4-bit adder using an unclocked process with a sensitivity list is process.4.bit.adder.vhd.  A process always has either a wait statement or a sensitivity list, but never both.  In this process, we are using a sensitivity list. The sensitivity list of an unclocked process should include the primary inputs to the process, that is to say the signals that are read in the process that are from outside of the process and that not generated inside of the process.  Since the signals, addend_one, addend_two, and carry_in are read in the process and are from outside the process, they are included in the sensitivity list.  When the value of a signal in the sensitivity list changes, the process is executed.  In the process, carry is declared as a five-bit variable.  The variable assignment operator is :=.  A variable changes value instantaneously when written to, whereas a signal, when assigned a value, is scheduled to change a delta cycle later.  Delta cycles will be examined in section 7 of this tutorial.  A variable can only be declared inside a process , function, or a procedure.  When writing to a variable,that is to say that a variable is on the left-hand side of the assignment operator, you should use the variable assignment operator.  When writing to a signal, you should use signal assignment operator, <=. A variable can read either the value of a signal or a variable. Likewise, a signal can read either the value of a signal or a variable. You should use caution when using both signals and variables, since variables change value instantaneously when assigned to, while signals are scheduled to change value at the next delta cycle when assigned to. A signal can only be assigned a value once when a process is executed. If a signal is assigned twice in a process execution, it will always get the second value.

6.  Delta cycles and processes

a,b,x,y, and z received the initialization values in delta cycle 0.  This change fired processes p1 and p2 and at the end of delta +1, signals x,y, and z have changed from their value at the end of delta +0.  The change in y fired p1 and the change in x fired p2 in delta +2 and x and z changed their value in delta +2.  Since y did not change in delta +2 and y is the only signal in the sensitivity list of p1, p1 did not fire in delta +3.  However, since x did change value in delta +2 and it is in the sensitivity list of p2, p2 fired in delta +3.  The signal z is the only signal that changed in delta +3 and since z is not in any sensitivity list, neither process fired and we received the message "Nothing left to do".

To write your List data to a file , from the List menu, choose File | Write List (tabular).  When the Write List window opens, enlarge it so that you can view it properly, type in a name for the file, and choose Save.   To set the printer destination, in a xterm window, use the command,  setenv printername.  To print, since this is a text file, you can use the command, lp list.lst  in the xterm window assuming you named the file containing the list data, list.lst.

Another example of delta cycles can be seen by compiling infinite.vhd and stepping through the simulation of the infinite_loop entity.  Signals y and z are initialized in delta +0.  This fires processes p1 and p2, which assign new values to y and z at delta +1.  This fires processes p1 and p2, which assign new values to y and z at delta +2.  We have an infinite loop.  The signal updating queue and the process firing queue are never simultaneously empty.  After 5 deltas, your List window should look as below. 

7.  Built-in functions

8.  FSMs

• Moore state machine:  moore.vhd.  The value of output Z depends on the value of CURRENT_STATE.  The fsm is composed of two processes.  One unclocked process is used to hold the combinational elements and one clocked process is used to hold the synchronous elements.  The process to hold the combinational elements uses a sensitivity list which is comprised of signals read in the process, X and CURRENT_STATE.  Signals assigned to in unclocked processes are synthesized as wires if no memory is inferred or as latches if memory is inferred.  In this unclocked process, Z and NEXT_STATE are synthesized as wires. The clocked process to hold the sequential elements has a sensitivity list that includes the clock signal and the reset signal.  When the value of the signal CLK changes from 0 to 1, CURRENT_STATE is scheduled to be assigned the value of NEXT_STATE.  Signals assigned to in a clocked process, if synthesized to hardware, are synthesized as registers.  CURRENT_STATE is synthesized as the state register of the state machine. This state machine uses state machine design style 1.

  In a clocked process when you want to represent a register, you should use a signal, not a variable.  Since a register is only updated on the rising edge of the clock or on reset, you want to use a signal since a signal is scheduled to change.  A variable is changed instantaneously, which would not accurately depict the correct functionality of a register.  The pre- and post- synthesis simulations would not correspond to each other.  A clocked process should only include the clock signal and a reset signal and possibly an enable signal in the sensitivity list; no other signals should be included.

• Mealy state machine:  mealy.vhd.  The output value Z depends on both the value of CURRENT_STATE
and the value of the input X.

A sample VHDL testbench for the moore state machine is provided:  tb_moore.vhd.   Suppose that you want to view on the wave timing diagram the six signals: RESET, X, CLK, Z, NEXT_STATE, and CURRENT_STATE.

One method to do this is to use a .do macro file.  Another method is to use the window menus.

• To use a .do macro file for the moore state machine, the steps are:
  
  
  1. Copy the .do file, moore.do to the directory that you are running vsim.
     
     
  2. Load the tb_moore entity into vsim.
     
     
  3. In the vsim transcript window, type the command, do moore.do
  
  
  
• To use the window menus for the moore state machine, the steps are:
  
  
  1. From the ModelSim vsim transcript window menu, choose View Structure.
     
     
  2. From the ModelSim vsim transcript window menu, choose View Signals.
     
     
  3. From the ModelSim vsim transcript window menu, choose View Wave.
     
     
  4. In the Structure window, click on uut: moore.
     
     
  5. The five signals of interest will be displayed in the Signals window.
     
     
  6. From the Signals window menu, choose View Wave > Signals In Region.
     
     
  7. The five signals of interest will be displayed in the wave timing diagram.

To generate a .do macro file, open vsim and use the sequence of menu choices and/or commands in the vsim windows that you wish to place in the macro file.  In the directory in which vsim was opened, there will be a file called transcript.  That file contains the vsim commands that correspond to the sequence of menu choices and/or commands that were used.  The file, transcript, can be copied to a .do file and used as a macro file.

9.  Counter example

• An example of the use of a function in VHDL is the counter source code, sync_reset_counter.vhd.  In the process called count_up, a function named incr is called to increment.  The function is defined in the package,count_type, which is contained in the file,count_pack.vhd.
• A sample VHDL test bench is  tb_src.vhd.

10.  Register file example

11.  Functional rtl

12.  A few notes

1. Unix note.
2. Cpu limit note.
3. Latch note.
4. Combinational loop note.
5. Explicit option note.
6. Integer note.
7. -93 compile option note.

13.  Synthesis preparation and startup

1. full.adder.vhd
   
   
2. h.4.bit.adder.vhd

1. unlimit
   
   
2. prep leonardo
   
   
3. leonardo   &
   
   
4. Select the default of Leonardo Spectrum 3 as the license to check out when that window appears and select ok.
   
   
5. From the Leonardo menu, select Tools => Flowtabs.

14.  Specification and Loading of the technology library

1. Select the Technology tab.
   
   
2. Select the + next to FPGA/CPLD.
   
   
3. Select the + next to Xilinx.
   
   
4. Select X4000E.
   
   
5. In the Device field scroll down to 4025ePG223.  The speed field should be set to -2 and the wire load should be set to 4025e-2_avg.
   
   
6. Select the Load Library button.

15.  Reading In Your VHDL Source Files

1. Select the Input tab.
   
   
2. Then select the open file icon.  The Set Input File(s) window will open. 
   
   
3. Browse to full.adder.vhd. 
   
   
4. Select full.adder.vhd.
   
   
5. Select "Open".  The Set Input File(s) window will close.
   
   
6. Then select the open file icon.  The Set Input File(s) window will open. 
   
   
7. Browse to h.4.bit.adder.vhd. 
   
   
8. Select h.4.bit.adder.vhd.
   
   
9. Select "Open".  The Set Input File(s) window will close.
   
   
10. On the Input flowtab page, Select "Read".
    
    
11. The act of reading in the file performs syntax checking of the file.   There should be no errors.  Errors in the transcript window are designated with a red circle.  Warnings are designated with a blue circle.  Information is designated with a green circle.  If you have an error, read the error message and try to correct the error.  By double clicking on the red circle, your source code will open with the red circle marking the problematic code.

16.  Optimization

1. Select the "Constraints" tab. 
   
   
2. Select "Specify Clock Period".  Specify 20 ns.  Select "Apply". 
   
   
3. Select the Optimize tab.  Choose "Optimize For: Delay".  Select the "Optimize" button.  Your design will be mapped and optimized to the Xilinx X4000E FPGA technology library.

17.  Writing An EDIF Output File

1. Select the "Output" tab.
   
   
2. Select edif.
   
   
3. Select write.
   
   
4. An .edf file will be written to the file specified in the filename space.

18.  The Resource Report

1. Select the "Report" tab. 
   
   
2. Type h4ba.resources in the "Report File Name" box. 
   
   
3. Select the "Report Area" button.  A resource report will be written to the file, h4ba.resources, in the directory in which you opened Leonardo.

19.  The Delay Report

1. Select the "Report" tab. 
   
   
2. Select the "Delay Report" tab near the bottom of the Leonardo window. 
   
   
3. Type h4ba.delay in the "Report File Name" box. 
   
   
4. Select the "Report Delay" button.  A delay report will be written to the file, h4ba.delay, in the directory in which you opened Leonardo.

20.  Synthesis Script Method

1. At a unix shell prompt, type,
   unlimit
   
   
2. At a unix shell prompt, type,
   prep  leonardo
   
   
3. At the unix shell prompt, type,
   spectrum
   which will invoke Leonardo Spectrum in batch-mode.
   
   
4. At the spectrum prompt, type,
   source  h4ba.synthesis.script
   To execute this file successfully, you should have the files, full.adder.vhd and h.4.bit.adder.vhd in the directory in which you are running the script.

21.  Xilinx placement and routing

22.  Gate-level simulation

1. Select a Unix workstation.



2. Make a new unix directory, tutorial3.dir.



3. Copy the modelsim.ini file to your new unix directory.



4. Copy the time_sim.vhd file generated in the Xilinx run to your new unix directory.



5. Copy the time_sim.sdf file generated in the Xilinx run to your new unix directory.



6. Copy tb_h4ba.vhd to tutorial3.dir.  This file is a testbench from earlier in the tutorial, but with the std_ulogic and std_ulogic_vector changed to std_logic and std_logic_vector.  This is so there will be no type incompatability with the time_sim.vhd file produced by Xilinx which uses std_logic and std_logic_vector. 



7. Copy tutorial3.makefile to tutorial3.dir.



8. Copy tutorial3.do to tutorial3.dir.



9. Type the command, 
   prep mentor



10. Type the command, 
    chmod   u+x   tutorial3.makefile
    The last line of tutorial3.makefile enables annotation of maximum timing values from the SDF file time_sim.sdf to the instance UUT under the top-level entity tb_h4ba.  The line also executes the macro file tutorial3.do in the gate-level simulation.



11. Type the command, 
    tutorial3.makefile



12. The gate-level simulation of the 4-bit adder will be displayed in the wave timing window in vsim.